1. Field of the Invention
The present invention relates to a data read method of a magnetic random access memory (MRAM).
2. Description of the Related Art
Magnetic random access memories (MRAMs) having magnetic tunnel junction (MTJ) elements which use a tunneling magnetoresistive (TMR) effect have been proposed recently. Such a magnetic random access memory is disclosed in, e.g., Roy Scheuerlein et al., “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, 2000 ISSCC 2000 Digest of Technical Papers, (USA), February 2000, pp. 128–129).
FIG. 103 is a schematic sectional view of a one-transistor, one-MTJ-element (1 Tr+1 MTJ) memory cell of a conventional magnetic random access memory. As shown in FIG. 103, a 1 Tr+1 MTJ memory cell includes an MTJ element MTJ arranged at the intersection of a bit line BL and a write word line WWL and a MOS transistor Tr serving as a read switching element electrically connected to the MTJ element MTJ.
The MTJ element MTJ includes a fixed layer 13, tunnel barrier layer 14, and free layer 15. A thin insulating film (tunnel barrier layer 14) is sandwiched between two magnetic thin films (fixed layer 13 and free layer 15).
The bit line BL is connected to the free layer 15 of the MTJ element. A read line RL is connected to the fixed layer 13 of the MTJ element. The write word line WWL is electrically disconnected from the MTJ element. One source/drain diffusion layer S/D of the MOS transistor Tr is connected to the fixed layer 13 of the MTJ element through a contact, wiring, and read line RL. The other source/drain diffusion layer S/D of the MOS transistor Tr is connected to a ground line GL through a contact.
In this magnetic random access memory, the MTJ element is used as an information storage element which stores “1” or “0” data on the basis of the following principle.
The MTJ element can create two states, i.e., a state in which the directions of magnetization in the fixed layer 13 and free layer 15 are parallel and a state in which the magnetization directions are anti-parallel. When the Magnetization directions are parallel, the tunnel resistance flowing through the tunnel barrier layer 14 is lowest. In this state, “0” data can be stored. When the magnetization directions are anti-parallel, the tunnel resistance flowing through the tunnel barrier layer 14 is highest. In this state, “1” data can be stored. The write and read operations of “1” and “0” data are executed in the following way.
To write “1” or “0” data in the MTJ element, a pair of write word line WWL and bit line BL is selected for an arbitrary selected cell. Write currents are supplied to both the selected write word line WWL and bit line BL. A current magnetic field generated by the write currents of the write word line WWL and bit line BL is applied to the MTJ element of the selected cell. Depending on whether the magnetization in the free layer 15 of the MTJ element reverses in excess of the reversal threshold value, “1” or “0” data is written. Since the write word line WWL is electrically isolated, no voltage is applied to the MTJ element in the write. Hence, breakdown of the element can be suppressed.
To read out “1” or “0” data written in the MTJ element, the bit line BL connected to one terminal of the MTJ element is selected. The gate electrode (read word line RWL) of the MOS transistor Tr connected to the other terminal of the MTJ element is turned on. A read current is supplied from the bit line BL to the ground line GL. The resistance state of the MTJ element is read out, thereby discriminating the state of the MTJ element. When the data of an arbitrary MTJ element is read out in this way, sneak read current to another MTJ element can be prevented. Hence a high read signal margin can be obtained.
In the 1 Tr+1 MTJ memory cell described above, the MTJ element and MOS transistor are connected in a one-to-one correspondence. Since the sizes of the read line RL and MOS transistor Tr affect the cell size, it is difficult to form a small cell. It is also difficult to actually reduce the cell area by forming a multilayered structure.
As a solution to this problem, a ladder-shaped cell structure has been proposed in which MTJ elements of two or more bits are connected in parallel (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-110933). In this ladder-shaped cell structure, the read current is supplied at once to MTJ elements connected in parallel. Hence, only one MOS transistor is necessary for the MTJ elements connected in parallel. For this reason, the larger the number of MTJ elements connected in parallel becomes, the smaller the actual cell area can be made.
However, in the read operation of the ladder-shaped cell structure, the read current flows not only to the selected cell but also to the remaining cells connected in parallel to the same bit line as that of the selected cell. For this reason, to read out the state of the selected cell, an expected value is written in the selected cell. After the data is discriminated, the write operation is executed again to return to the initial state. That is, a complex read operation of four cycles is necessary. Hence, the time required for the write operation becomes long inevitably and impedes practical use.